This application claims priority from Korean Priority Document No. 2001-65522, filed on Oct. 23, 2001, which is hereby incorporated by reference in its entirety.
1. Technical Field
This disclosure relates to a high voltage generating circuit, and more particularly, to a high voltage generating circuit for a semiconductor memory device.
2. Background
A high voltage generating circuit for a semiconductor memory device generally generates a high voltage this is higher than a power voltage that is externally provided. The high voltage generating circuit is used to transfer a signal having a power voltage level without causing a threshold voltage loss when a high voltage generated therefrom is applied to a gate of an NMOS transistor that is a component of circuits such as a word line driver, a bit line isolation circuit, or a data output buffer.
A memory cell of a conventional dynamic semiconductor memory device includes a capacitor for storing a data and an NMOS transistor that turns on in response to a signal applied to a word line to transfer data between a bit line and the capacitor. However, the NMOS transistor has a disadvantage in that a threshold voltage loss occurs when a signal having a power voltage level is transferred. Hence, a high voltage is applied to the word line in response to an active command in order to transfer data without causing a threshold voltage loss.
FIG. 1 is a circuit diagram illustrating a conventional high voltage generating circuit. The high voltage generating circuit of FIG. 1 includes a pulse signal generating circuit 10, NMOS transistors N1, and N2-1 to N2-n, and CMOS capacitors C11 to C1n. 
The pulse signal generating circuit 10 repeatedly generates pulse signals P1 and P2 which have a phase opposite to each other. Each of the capacitors C11 to C1n steps up nodes n1 to nn in response to the pulse signals P1 and P2. The NMOS transistor N1 is diode connected and transfers a voltage VDDxe2x88x92VT to the node n1. The NMOS transistors N2-1 to N2-n transfer voltages of the nodes n1 to nn to the nodes n2 to nn and a high voltage generating terminal in response to voltages applied to the nodes n1 to nn, respectively.
Operation of the high voltage generating circuit of FIG. 1 is described with reference to a timing diagram of FIG. 2.
The node n1 is pre-charged to a voltage level VDDxe2x88x92VT. Here, the voltage VT represents a threshold voltage level of the NMOS transistor N1.
During a time period T1, the odd nodes n1 and n(nxe2x88x921) are boosted to a voltage level VDDxe2x88x92VT in response to the pulse signal P1 having a logic xe2x80x9chighxe2x80x9d level. The boosted voltage is transferred to the even nodes n2 and nn through the NMOS transistors N2-1 to N2-(nxe2x88x921). The even nodes n2 and nn become pumped to a voltage level 2 VDDxe2x88x922 VT.
During a time period T2, the even nodes n2 and nn are boosted to a voltage level 3 VDDxe2x88x922 VT. The boosted voltage is transferred to the nodes n3 (not shown) to n(nxe2x88x921) and the high voltage generating terminal through the NMOS transistors N2-2 to N2-n. The nodes n3 to n(nxe2x88x921) and the high voltage generating terminal become a voltage level 3 VDDxe2x88x923 VT.
However, the high voltage generating circuit of FIG. 1 has to experience an n-number of stages so as to boost a high voltage VPP. Therefore, power consumption is increased, and the high voltage cannot be generated fast within a desired time.
FIG. 3 is a schematic view illustrating another conventional high voltage generating circuit. The high voltage generating circuit of FIG. 3 includes a control signal generating circuit 20, pre-charge circuits 22 and 24, capacitors C2 and C3, level shifters 26 and 28, and NMOS transistors N3 and N4.
The high voltage generating circuit of FIG. 3 shows a configuration illustrating a two-stage step-up circuit having a pre-charge circuit.
The control signal generating circuit 20 generates a pulse signal P3 having a phase opposite to an active command ACT, and generates pulse signals P4 and P5 which have a phase opposite to each other when the active command ACT having a logic xe2x80x9chighxe2x80x9d level is applied. The pre-charge circuits 22 and 24 pre-charge nodes A and B in response to the pulse signal P3, respectively. The capacitors C2 and C3 step up the nodes A and B in response to the pulse signals P4 and P5, respectively. The NMOS transistors N3 and N4 are turned on in response to output signals of the level shifters 26 and 28 to transfer voltages of the nodes A and B.
Operation of the high voltage generating circuit of FIG. 3 is described with reference to a timing diagram of FIG. 4.
During a time period T3, when the active command ACT having a logic xe2x80x9clowxe2x80x9d level is applied, the pulse signal P3 having a logic xe2x80x9chighxe2x80x9d level is generated from the control signal generating circuit 20. The pre-charge circuits 22 and 24 pre-charge the nodes A and B to a voltage level VDD when the pulse signal P3 having a logic xe2x80x9chighxe2x80x9d level is generated.
During a time period T4, when the active command ACT having a logic xe2x80x9chighxe2x80x9d level is applied, the control signal generating circuit 20 generates the pulse signal P4 having a logic xe2x80x9chighxe2x80x9d level. When the pulse signal P4 having a logic xe2x80x9chighxe2x80x9d level is generated, a voltage of the node A is boosted to a voltage level 2 VDD by the capacitor C2. The level shifter 26 shifts a voltage level of the pulse signal P4 from a power voltage (VDD) level to a high voltage level. The NMOS transistor N3 is turned on in response to the high voltage level. As a result, a charge sharing operation is performed between the nodes A and B so that the voltages of the nodes A and B become a voltage level 1.5 VDD.
During a time period T5, the pulse signal P4 having a logic xe2x80x9clowxe2x80x9d level and the pulse signal P5 having a logic xe2x80x9chighxe2x80x9d level are generated from the control signal generating circuit 20. When the pulse signal P5 having a logic xe2x80x9chighxe2x80x9d level is generated, a voltage of the node B is boosted to a voltage level 2.5 VDD by the capacitor C3. The level shifter 28 shifts a voltage level of the pulse signal P5 from the power voltage level to the high voltage level. The NMOS transistor N4 is turned on in response to the high voltage level. As a result, the charge sharing operation is performed between the node B and the high voltage generating terminal so that a level of the high voltage is boosted.
The high voltage generating circuit of FIG. 3 can boost a voltage of the node B, which is a voltage-boosting node, to a voltage level 2.5 VDD. That is, the high voltage generating circuit of FIG. 3 can boost a voltage of the voltage-boosting node higher than that of FIG. 1 and is faster in voltage-boosting timing than that of FIG. 1.
The high voltage generating circuit of FIG. 3 has no problem when the power voltage is high. However, as a level of a power voltage VDD of the semiconductor memory device is decreased due to lower power level requirements, a level of the high voltage VPP is decreased. Therefore, since the decreasing of the power voltage VDD is greater than the decreasing of the high voltage VPP, it is not easy to generate a high voltage VPP having a desired level by the high voltage generating circuit of FIG. 3.
Embodiments of the present invention provide a high voltage generating circuit and method which can quickly boost the high voltage to a desired level even though a level of a power voltage is lowered.